Field of the Invention
The invention relates to an integrated circuit configuration having at least one transistor and one capacitor, and also to a method for fabricating it.
With regard to ever faster components at a higher integration level, the feature sizes of integrated circuit configurations decrease from generation to generation. At the present time, the integrated circuit configurations are usually realized using a planar silicon technology in which the components are disposed next to one another and are connected to one another via a plurality of metallization planes.
If an integrated circuit configuration contains a transistor, then its packing density can be increased by configuring the transistor as a vertical transistor. The reference by L. Risch et al., titled xe2x80x9cVertical MOS-Transistors With 70 nm Channel Lengthxe2x80x9d, ISSDERC 1995, pages 101 to 104, describes vertical MOS transistors in which, in order to fabricate them, layer sequences having layers corresponding to source, channel and drain are formed and are annularly surrounded by a gate electrode.
A further possibility for increasing the packing density of an integrated circuit configuration consists in disposing two components one above the other. German Patent DE 195 19 160 C1 proposes a dynamic random access memory (DRAM) cell configuration in which a storage capacitor is disposed above a selection transistor. A first source/drain region, a channel region disposed underneath and a second source/drain region, disposed underneath, of the selection transistor are parts of a projection-like semiconductor structure which is annularly surrounded by a gate electrode. Mutually adjoining gate electrodes form word lines. The first source/drain region also acts as a first capacitor electrode of the storage capacitor. A capacitor dielectric is disposed over the first capacitor electrode, and a second capacitor electrode is disposed over the capacitor dielectric, the second capacitor electrode acting as a common capacitor plate for all the storage capacitors of the DRAM cell configuration. The area of a memory cell of the DRAM cell configuration may be 4F2, where F is the minimum feature size that can be fabricated in the technology used.
It is accordingly an object of the invention to provide an integrated circuit configuration having at least one transistor and one capacitor, and a method for fabricating it, that overcome the above-mentioned disadvantages of the prior art methods and devices of this general type.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated circuit. The integrated circuit contains a transistor having a first source/drain region and a second source/drain region, and a capacitor having a dielectric layer, a first capacitor electrode, and a second capacitor electrode adjoining the dielectric layer. An insulating layer is provided and a patterned conductive layer is disposed above the insulating layer. A structure through which the transistor can be driven is disposed beneath the patterned conductive layer, the insulating layer isolating the structure from the patterned conductive layer. A vertical conductive structure having a first region, a second region and a third region disposed one above another with respect to a vertical axis is provided, the second region is disposed between the first region and the third region. The first region of the vertical conductive structure laterally adjoins the conductive layer, and the third region of the vertical conductive structure adjoins the first source/drain region of the transistor. The patterned conductive layer and the vertical conductive structure together form the first capacitor electrode of the capacitor, and the dielectric layer adjoins the vertical conductive structure and the conductive layer. An insulating structure laterally adjoins the structure through which the transistor can be driven. The second region of the vertical conductive structure laterally adjoins the insulating structure.
The invention is based on the problem of specifying an integrated circuit configuration having at least one transistor and one capacitor in which the first source/drain region of the transistor is connected to the first capacitor electrode of the capacitor, in which the capacitor has a high capacitance and which can nevertheless be fabricated with a high packing density.
In the case of an integrated circuit configuration according to the invention, a structure via which the transistor can be driven and the patterned conductive layer which is part of the first capacitor electrode of the capacitor are disposed one above the other. An insulating layer isolates the structure via which the transistor can be driven from the conductive layer. Disposing the conductive layer and the structure via which the transistor can be driven one above the other increases the packing density of the circuit configuration compared with embodiments of the prior art, in which the first capacitor electrode and the structure via which the transistor can be driven are disposed next to one another.
A vertical conductive structure is provided as a further part of the first capacitor electrode. Which structure, having a first region, laterally overlaps the conductive layer, is insulated, at a second region, by an insulating structure from the structure via which the transistor can be driven, and, with a third region, overlaps a first source/drain region of the transistor. The second region is disposed between the first region and the third region. The first region, the second region, and the third region of the vertical conductive structure are disposed one above the other with respect to a vertical axis, that is to say an axis that is vertical with respect to the layer planes. The insulating structure laterally adjoins the structure via which the transistor can be driven. The second region of the vertical conductive structure laterally adjoins the insulating structure. A capacitor dielectric adjoins the conductive layer and the vertical conductive structure, and is in turn adjoined by a second capacitor electrode of the capacitor. On account of the vertical conductive structure, an effective surface area of the first capacitor electrode is greater than its projection onto a horizontal plane, which is highly advantageous since a capacitance of the capacitor can be increased without reducing the packing density of the circuit configuration.
Furthermore, a particularly high packing density of the circuit configuration results from the fact that at least one sidewall of the structure via which the transistor can be driven is utilized for enlarging the surface area of the first capacitor electrode.
Moreover, it is advantageous that the vertical conductive structure allows the connection between the first source/drain region of the transistor and the conductive layer even though, in terms of the height, that is to say with respect to the vertical axis, the structure via which the transistor can be driven is disposed between them.
A xe2x80x9cspacerxe2x80x9d is understood to be a structure formed on a lateral area of an at least approximately step-shaped structure when material is deposited essentially conformally and etched back anisotropically until horizontal areas of the step-shaped structure are uncovered.
It is advantageous to configure the vertical conductive structure as a spacer since the spacer has a small horizontal dimension, and a particularly high packing density can thus be attained. The connection between the first source/drain region of the transistor and the conductive layer occupies a particularly small horizontal area, which is why a horizontal cross section of the capacitor or of the first source/drain region may also turn out to be small.
The transistor may be disposed higher than the conductive layer. In this case, the third region of the vertical conductive structure is disposed higher than the first region of the vertical conductive structure.
The transistor may be disposed at a greater depth than the conductive layer. In this case, the first region of the vertical conductive structure is disposed higher than the third region of the vertical conductive structure.
The structure via which the transistor can be driven may be a gate electrode of the transistor. In this case, the gate electrode is disposed, in the vertical direction, between a channel region of the transistor, the channel region being provided with a gate dielectric, and the capacitor. The channel region is disposed, in the horizontal direction, between the first source/drain region and a second source/drain region of the transistor. The conductive layer is disposed over the transistor, and, with a lower, essentially horizontal area, the third region of the vertical conductive structure adjoins the first source/drain region.
As an alternative, the structure via which the transistor can be driven is not the gate electrode per se but rather is merely connected to the gate electrode. In this case, the structure via which the transistor can be driven may be disposed between the first source/drain region and the capacitor. The transistor and the conductive layer are thus disposed one above the other. The structure via which the transistor can be driven is isolated from the first source/drain region by a further insulating layer.
A particularly high packing density can be attained if the vertical conductive structure adjoins a first sidewall of the first source/drain region and a first sidewall of the first capacitor electrode.
If the first source/drain region projects beyond the insulating structure in the horizontal direction in the third region of the vertical conductive structure, and if the first source/drain region is located at a greater depth than the conductive layer, then, with its lower area, the third region of the vertical conductive structure may adjoin the first source/drain region. Conversely, with its lower area, the first region may adjoin the conductive layer if the conductive layer projects beyond the insulating structure in the horizontal direction in the first region of the vertical conductive structure and the capacitor is located at a greater depth than the first source/drain region.
In order that the horizontal dimension of the vertical conductive structure may be as small as possible and can overlap the first sidewall of the first source/drain region and the first sidewall of the conductive layer, it is advantageous if the sidewalls are essentially parallel to one another and do not have an excessively large spacing from one another in the horizontal direction. The spacing is preferably approximately equal to the horizontal dimension of the insulating structure.
In order to increase the packing density, it is advantageous if the horizontal dimension of the insulating structure is small. The insulating structure is in the form of a spacer, for example. As an alternative, the insulating structure can be produced by thermal oxidation of a sidewall of the structure via which the transistor can be driven on which the vertical conductive structure is disposed.
If the transistor is located at a greater depth than the conductive layer, then care must be taken, particularly in the case of thermal oxidation, to ensure that the insulating structure does not cover the entire first source/drain region, since otherwise the vertical conductive structure cannot directly adjoin the first source/drain region. One possibility for ensuring this consists in producing the first source/drain region after the production of the insulating structure by patterning a conductive region, etching being effected selectively with respect to the insulating structure. As a result, the first sidewall of the first source/drain region is produced after the production of the insulating structure, and the vertical conductive structure can be produced in a manner adjoining the first source/drain region. If the first sidewall of the conductive layer and the sidewall of the structure via which the transistor can be driven lie in the same plane, then the first sidewall of the conductive layer and the first sidewall of the first source/drain region do not lie in the same plane, since etching is effected selectively with respect to the insulating structure which adjoins the sidewall of the structure via which the transistor can be driven, and has a finite horizontal dimension.
The conductive region may be realized e.g. as a doped region in a substrate containing semiconductor material.
An advantageous method is described below in which the capacitor, the structure via which the transistor can be driven, and the first source/drain region are produced one above the other in a self-aligned manner, that is to say without the use of masks to be aligned.
The conductive region is produced at a surface of the substrate. At least a first insulating layer, a first conductive layer, a second insulating layer and a second conductive layer, which corresponds to the conductive layer mentioned above, are produced. A depression that cuts through at least the first conductive layer is produced. The first insulating layer may serve as an etching stop in this case. An insulating material is deposited and etched back to an extent such that the insulating structure in the form of a spacer is produced, which laterally covers the first conductive layer. The depression is deepened, so that the region is cut through, etching being effected selectively with respect to the insulating structure. The vertical conductive structure is produced by depositing and anisotropically etching back conductive material, which structure overlaps the region, the insulating structure and the second conductive layer. The first capacitor electrode of the capacitor is produced form the second conductive layer and the vertical conductive structure, the structure via which the transistor can be driven is produced from the first conductive layer, and the first source/drain region of the transistor is produced from the region. The deeper the depression, the larger the surface area of the first capacitor electrode and the higher the capacitance of the capacitor.
If the integrated circuit configuration is a memory cell configuration, e.g. a DRAM cell configuration, then the structure via which the transistor can be driven may be a word line. Memory cells of the memory cell configuration each contain a transistor and a capacitor, which are connected to one another via a vertical conductive structure. A second source/drain region of the transistor is connected to a bit line.
As an alternative, the structure via which the transistor can be driven serves for connecting the transistor to another component.
It is advantageous to configure the transistor as a planar transistor since it is possible to use the standard technology for producing the transistor in this case.
In order to increase the packing density, it is advantageous if the transistor is configured as a vertical transistor, The transistor is disposed under the conductive layer, for example. In this case, a channel region of the transistor is disposed under the first source/drain region. The gate electrode is disposed on a continuationxe2x80x94formed by the channel regionxe2x80x94of a second sidewall of the first source/drain region. The gate electrode is isolated from the channel region by a gate dielectric and is connected to the structure via which the transistor can be driven.
It lies within the scope of the invention for the word line to run parallel to the first sidewall of the first source/drain region and to the surface of the substrate. In order to increase the packing density it is advantageous in this case if the second sidewall of the first source/drain region adjoins the first sidewall of the first source/drain region, the first sidewall being adjoined by the vertical conductive structure. The second sidewall of the first source/drain region is provided with insulation that electrically insulates the gate electrode from the first source/drain region. The gate electrode is disposed under the word line, which increases the packing density. The gate electrode may be produced together with the word line and is then a vertical protuberance of the word line.
The insulation and the gate dielectric may be contiguous and produced simultaneously. The insulation and the gate dielectric may be parts of the first insulating layer.
In order to reduce a capacitance formed by the gate electrode or the structure via which the transistor can be driven and the first source/drain region, it is advantageous, in the case where the insulation and the gate dielectric are parts of the first insulating layer, if parts of the first insulating layer which do not act as the gate dielectric are thicker than the gate dielectric. This is the case, for example, if the first insulating layer is produced by thermal oxidation, since the thermal oxidation progresses more rapidly in the region of more highly doped regions and the resulting oxide is thicker than in the case of lightly doped regions.
In order to simplify the process, in order to increase the capacitance of the capacitor and in order to improve contact-making, it is advantageous if a further vertical conductive structure which is analogous to the vertical conductive structure and connects the first source/drain region to the conductive layer adjoins a third sidewall of the first source/drain region, the third sidewall being opposite the first sidewall.
First trenches may be provided which run transversely with respect to the word line and which are disposed between the first source/drain regions of the transistors. The gate electrodes are disposed in the first trenches. In order that the gate electrode does not drive two different transistors, structures that prevent the formation of channels adjoin first sidewalls of the first trenches at least in the region of channel regions of the transistors. This is equivalent to saying that one of the structures which prevent the formation of channels adjoins a fourth sidewall of the first source/drain region, the fourth sidewall being opposite the second sidewall of the first source/drain region, and also adjoins the continuation of the source/drain region, the continuation being formed by the channel region.
The structures that prevent the formation of channels may be formed in the form of channel stop regions by the first sidewalls of the first trenches being doped, by inclined implantation, more highly than the channel regions. This can be done with or without a mask. If a mask is used, then it covers for example parts of the first sidewalls of the first trenches at which the gate electrodes are not disposed.
As an alternative, the structures that prevent the formation of channels may be produced from insulating material. To that end, the insulating material may be deposited in such a way that the first trenches are filled. Afterwards, the insulating material is removed, e.g. by a photolithographic method, at least from parts of the second sidewalls of the first trenches at which the gate electrodes are disposed, whereby the structures that prevent the formation of channels are produced.
A mask used in this process may be in strip form, its strips running parallel to the first trenches and covering the first sidewalls of the first trenches. As an alternative, the mask covers rectangular regions that do not overlap the parts of the second sidewalls of the first trenches at which the gate electrodes are disposed. This is particularly advantageous since, if the word lines are produced by depositing and patterning conductive material, the conductive material does not have to be etched as far as the bottoms of the first trenches.
In order that the word lines can be produced by depositing and patterning conductive material, it is advantageous for the insulating material with which the first trenches are filled to be planarized, before the production of the structures which prevent the formation of channels, until the surface of the substrate and thus the first source/drain regions are uncovered, and no insulating material is present outside the first trenches.
The depression in which the vertical conductive structure is disposed may be part of one of second trenches running transversely with respect to the first trenches. The first source/drain regions are isolated from one another by the first trenches and the second trenches. The word lines may be produced by the production of the second trenches. If, in this case, the strip-type mask is used in the production of the structures that prevent the formation of channels, then further depressions are produced in regions in which the first trenches and the second trenches intersect. It is advantageous to fill these further depressions by depositing and etching back insulating material.
An advantageous method is described below in which the capacitor, the word line and the first source/drain region are do produced one above the other in a self-aligned manner, that is to say without the use of masks to be aligned. A region containing strips disposed between the first trenches is produced at the surface of the substrate. After the production of the structures that prevent the formation of channels, and of the first insulating layer which partly acts as a gate dielectric and which also covers the surface of the substrate, a first conductive layer is deposited. Over the first conductive layer, a second insulating layer is deposited, and over the latter a second conductive layer is deposited. The production of the second trenches reaching down to the first insulating layer results in the word lines being produced from the first conductive layer. After the production of the second trenches, an insulating material is deposited and etched back, thereby producing the insulating structures in the form of spacers. Afterwards, the second trenches are deepened, etching being effected selectively with respect to the insulating structures. The region is cut through in the process. The first source/drain regions are produced from the region. If the insulating structures cover sidewalls of the patterned second conductive layer, the insulating structures are etched back until the sidewalls are at least partly uncovered. In order to produce the vertical conductive structures, conductive material is deposited and etched back. The vertical conductive structures cover the sidewalls of the second conductive layer and the first and third sidewalls of the first source/drain regions. Afterwards, the second conductive layer and the vertical conductive structures are patterned with the aid of a mask corresponding to the mask for producing the first trenches. In the process, the mutually isolated first capacitor electrodes are produced from the second conductive layer and the vertical conductive structures. Two of the vertical conductive structures in each case make contact with parts of the patterned second conductive layer. The same applies to the first source/drain regions. A capacitor dielectric is deposited over the first capacitor electrodes and further conductive material is deposited over the capacitor dielectric, the material forming a second capacitor electrode which is common to all the capacitors of the memory cell configuration.
To ensure that the second conductive layer is not attacked when the second trenches are deepened, it is advantageous to produce an auxiliary layer over the second conductive layer. Etching is effected selectively with respect to the auxiliary layer in the course of the deepening process.
To ensure that a potential at the second capacitor electrode does not produce any channels between the first source/drain regions which are adjacent to one another transversely with respect to the word line, an implantation may be carried out before the production of the second capacitor electrode or of the vertical conductive structures. As a result of which channel stop structures in the form of further channel stop regions, which are doped more highly than the channel regions, are produced at least at bottoms of the second trenches. As an alternative, the channel stop structures are produced from insulating material in the form of further insulating structures which adjoin the bottoms of the second trenches, by the second trenches being deepened to a particularly great extent and being partly filled e.g. by depositing and etching back the insulating material. The channel stop structures do not completely fill the deepened parts of the second trenches, in order that the vertical conductive structures can make contact with the first source/drain regions.
A second source/drain region of the transistor may be disposed underneath the channel region or in a manner offset diagonally downward with respect to the channel region, that is to say laterally with respect to, and at a greater depth than, the channel region. In the first case, the first trenches and/or the second trenches can pattern a layer sequence corresponding to source, channel and drain regions. In the second case, an implantation can be carried out after the production of the first trenches, whereby the second source/drain region is produced at bottoms of the first trenches. If the integrated circuit configuration is a memory cell configuration, bit lines are produced along the bottoms of the first trenches, and partly act as second source/drain regions of the transistors.
The region from which the first source/drain regions are produced may be produced e.g. over the whole area and subsequently be patterned in strip form by the first trenches. As an alternative, the region is produced in the form of strips by implantation being effected after the production of the first trenches.
The memory cells may each be produced with an area of 4F2, where F is the minimum feature size that can be produced in the technology used.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an integrated circuit configuration having at least one transistor and one capacitor, and a method for fabricating it, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.